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| 4500 Series Integrated Infrared Transceiver Module IrDA (SIR) Features D Compliant to IrDA 1.0 Standard D Two Package Options - S Option - Side View - T Option - Top View D Wide Supply Voltage Range (2.7 V - 5.5 V) D IrDA Data Rates Up to 115.2 kbps Baud Rate D 0- to 3.0-m Range D Low Profile D Few External Components Required D Low Power Consumption D AGC for EMI Immunity D Open Collector IRED Driver Description The TFDS4500 and TFDT4500 are infrared transceivers for data communication systems. The transceivers are compliant to the IrDA standard and allow data rates up to 115 kbit/s. An internal AGC (Automatic Gain Control) ensures proper operation under adverse EMI conditions. The internal IRED driver can be connected by an external current control resistor to an independent unregulated power supply, VCC2. This adds circuit design flexibility and efficient serial drive capability for external IREDs for high power applications. Pin Configurations TFDT4500 1 2 3 4 5 6 7 8 IRED Anode IRED Cathode Txd (Input) Rxd (Output) NC VCC1 (Supply Voltage) SC (Sensitivity Control) GND TFDS4500 IRED 1 Cathode 2 Rxd 3 VCC1 GND 4 8 IRED Anode 7 Txd 6 5 SC NC Functional Block Diagram VCC1 Driver Amplifier Comparator Rxd SC Txd AGC Logic IRED Anode IRED Cathode Open Collector Driver GND Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70737. TEMIC Semiconductors S-51444--Rev. A, 14-Jul-97 1 Pre-Release Information 4500 Series Absolute Maximum Ratings Parameter Supply Voltage Range Voltage Range of IRED Drive Output Input Currents Output Sinking Current Power Dissipation Junction Temperature Ambient Temperature Range (Operating) Storage Temperature Range Soldering Temperature Average IRED Current Repetitive Pulsed IRED Current Peak IRED Current IRED Anode Voltage Transmitter Data Input Voltage Receiver Data Output Voltage Virtual source size Maximum Intensity for Class1 Operation of IEC 825 or EN60825 IIRED(DC) IIRED(RP) IIRED(PK) VIREDA VTxd VRxd d Method: (1-1/e) EN60825, 1.1.1.997 t < 90 ms, Duty Cycle < 20% t < 2 ms, Duty Cycle < 10% -0.5 -0.5 -0.5 2.5 2.8 400 Ptot TJ TA Tstg t = 20 s 0 -25 215 (See Derating Curve) Symbol VCC1 Test Conditionsa IRED anode pin, Txd LOW All pins except IRED cathode pin and IRED anode pin (See IRED Current) Minb -0.5 -0.5 Typc Maxb 6 6 10 Unit V mA 25 200 125 70 85 240 100 500 1 6 VCC + 0.5 VCC + 0.5 mm mW/sr V mA A _C mW Notes a. Reference point GND pin unless otherwise noted. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Current Derating 600 Maximum Duty Cycle 20% Peak operating current (mA) 400 200 Current derating as a function of the maximum forward current of IRED and maximum duty cycle. 0 0 20 40 60 80 100 120 140 Ambient Temperature TA (_C) 2 Pre-Release Information TEMIC Semiconductors S-51444--Rev. A, 14-Jul-97 4500 Series Specifications Parameter Transceiver Supported Data Rates Supply Voltage Range Supply Current, VCCl Pin Leakage Current of IR Emitter, IRED Anode Pin Transceiver Power On Settling Time VCCl IS IS Reduced Function Down to 2.5 V VCC1 = 5.5 V VCC1 = 2.7 V VCC1 OFF, Txd LOW, VCC2 = 6 V T = -25 to 85_C 2.4 2.7 5 1.3 1.0 0.005 115.2 5.5 2.5 1.5 0.5 50 T = "15_, SIR Mode, SC = LOW T = "15_, SIR Mode, SC = HIGH T = "90_, VCC = 5 V, SIR Mode T = "90_, VCC = 3 V, SIR Mode SC = HIGH or LOW Active, C = 15 pF, R = 2.2 kW Non-Active, C = 15 pF, R = 2.2 kW VOL < 0.8 V tr , tf tp C = 15 pF, R = 2.2 kW 2.4 kBits/s, Input Pulse Length 1.41 ms to 3/16 of Bit Length 115.2 kBits/s, Input Pulse Length 1.41 ms to 3/16 of Bit Length Output Level = 0.5 x VCC1 @ Ee = 0.040 W/m2 Output Level = 0.5 x VCC1 Over a period of 10 bit, 115.2 kBIT/s Recovery from last transmitted pulse to 1.1 x threshold sensitivity 100 20 1.41 1.41 1 VCC - 0.5 4 200 20 8 2 6.5 2 800 ms 0.5 0.006 3300 8000 kBit/s V mA mA ms Symbol Test Conditionsa Minb Typc Maxb Unit Receiver Minimum Detection Threshold I di Irradianced Maximum Detection Threshold Irradianced I di Logic Low Receiver Input Irradiance Output Voltage Rxd Output Current Rise and Fall Time Rxd Signal Electrical g Output Pulse O t t P l Width Eemin Eemax Eemax(low) VOL VOH 0.020 0.010 5000 15000 0.004 0.8 V mA ns 0.035 0.015 2 Wm-2 Output Delay Time (Rxd) e, f p y Jitterg Latency tdl tdt tj tL Transmitter Driver Current IRED Logic Low Transmitter Input Voltage Logic High Transmitter Input Voltage Output Radiant Intensity p y Angle of Half Intensity Peak Wavelength of Emission Halfwidth of Emission Spectrum Optical Rise/Fall Time Overshoot, Optical Rising Edge Peak-to-Peak Jitter tj Over a period of 10 bits, independent of information content. tR, tF 115.2-kHz Square Wave Signal Duty Cycle: 1.1 ID VIL (Txd) VIH (Txd) IeH IeL T lp 850 60 200 600 25 0.2 Current limiting resistor in series to IRED: RS = 8.2 W @ 5 VCC2 = 5 V, T = "15_ Logic Low Level "24 900 Current limiting resistor in series to IRED: RS = 8.2 W, VCC2 = 5 V 0 2.4 45 140 0.3 0.5 0.8 VCC 200 0.04 A V mW/sr mW/sr _ nm ns % ms Notes a. Unless otherwise specified TA = 25_C, VCC = 5 V. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. BER = 10-8 (IrDA Specification) e. tdl = delay of leading edge of output signal related to leading edge of optical input signal. f. tdt = delay of trailing edge of output signal related to trailing edge of optical input signal. g. Leading edge of output signal. TEMIC Semiconductors S-51444--Rev. A, 14-Jul-97 3 Pre-Release Information 4500 Series Pin Assignment and Description Pin "S" "T" Option Option 8 1 7 2 6 3 5 4 - 1 2 3 4 5 6 7 8 - Pin Name IRED Anode IRED Cathode Txd Rxd NC VCC1 SC GND Guide Pinsa Stand-off Pinsb IRED Anode Description IRED Cathode, internally connected to driver transistor Transmitter Data Input Receiver Data Output, push-pull CMOS driver output capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. No connection Supply voltage, 2.7 V to 5.5 V (Refer to 4000 Series Application Note for using VCC1 as shutdown pin) Sensitivity control Ground "S" Option--Guide Pins (two), for surface mounting "T" Option--Guide Pins (two), used only for through-hole mounting I/O O O I O Active LOW LOW HIGH LOW I HIGH Note a. Refer to application notes for connecting "S" option guide pins on PCB. b. Refer to application notes for connecting "T" option as a side view, through-hole device for wave soldering application. 4 Pre-Release Information TEMIC Semiconductors S-51444--Rev. A, 14-Jul-97 4500 Series TFDT, Top View Option E E1 A2 R1 A3 A1 Millimeters Dim A A1 Inches Typical 0.299 0.169 0.096 0.085 0.059 0.010 0.020 0.034 0.234 0.215 0.148 0.074 0.512 0.256 0.450 0.236 0.256 0.050 0.093 0.008 0.063 0.010 0.069 0.079 30_ 5_ 5_ Typical 7.6 4.3 2.45 2.15 1.5 0.25 0.5 0.86 5.95 5.45 3.75 1.8 13.0 6.5 11.43 6 6.5 1.27 2.35 0.2 1.6 0.25 1.75 2 30_ 5_ 5_ Tolerance (") 0.5 0.3 0.3 0.3 0.3 +0.1/ - 0.05 0.1 +0.14/ - 0.16 0.25 0.25 0.25 0.25 0.5 0.5 - 0.5 0.5 - 0.15 0.2 - - - - - 3_ 5 Tolerance (") 0.020 0.012 0.012 0.012 0.012 +0.004/ - 0.002 0.004 +0.0055/ - 0.0063 0.010 0.010 0.010 0.010 0.020 0.020 - 0.02 0.02 - 0.006 0.008 - - - - - 3_ 5 d (EJECTION MARKS FRONT & BACKSIDE C e E2 C1 A2 1 A3 A4 b C E4 E3 C1 D D1 D2 d E E1 E2 R4 E3 E4 e D D1 D2 e1 e2 R1 R2 R3 R4 1 2 3 R3 Tangential 3 e1 e2 A b R2 A4 2 TEMIC Semiconductors S-51444--Rev. A, 14-Jul-97 5 Pre-Release Information 4500 Series TFDS, Side View Option E E1 R1 A A2 A1 A3 A4 C C1 e Millimeters Inches d (EJECTION MARKS FRONT & BACKSIDE C3 E2 E3 E5 E4 q2 C2 q1 Tolerance Tolerance Typical (") (") Dim Typical A A1 A2 A3 A4 b c C C1 C2 C3 D D1 5.3 4.3 2.85 3.15 1.5 0.25 0.15 0.5 0.16 0.58 0.86 5.95 5.45 3.75 1.8 13.0 6.5 11.43 11.75 6 6.5 1.27 2.35 6.7 1.6 0.2 1.75 2.0 30_ 15_ 180_ 5_ 5_ 90_ 0.6 0.3 0.3 0.3 0.3 - +0.1/-0.05 0.1 0.1 - +0.3/-0.2 +0.14/-0.16 0.25 0.25 0.25 0.5 0.5 - - 0.5 0.5 - 0.15 0.4 - - - - - - -6_ 5 3_ 2_ 0.2 0.209 0.169 0.112 0.124 0.059 0.010 .0059 0.020 0.006 0.023 0.034 2.34 0.215 0.148 0.074 0.512 0.256 0.450 0.463 0.236 0.256 0.050 0.093 0.264 0.063 0.008 0.069 0.0787 30_ 30_ 180_ 5_ 5_ 90_ 0.024 0.012 0.012 0.012 0.012 - +0.004/ -0.002 0.004 0.004 - +0.012/ -0.008 +0.0055/ -0.0063 0.110 0.010 0.010 0.010 0.020 0.020 - - 0.02 0.02 - 0.006 0.016 - - - - - - -6_ 5 3_ 2_ -0.008 R3 Tangential D D1 D2 q4 R4 D2 d E E1 E2 E3 E4 E5 e e1 q6 R2 c q5 e2 R1 R2 R3 R4 q1 q2 q3 q4 q5 q6 L L b e1 e2 q3 6 Pre-Release Information TEMIC Semiconductors S-51444--Rev. A, 14-Jul-97 4500 Series Recommended SMD Pads for Transceiver 1.27 TFDT 0.7 1.4 1 2 3 4 8.89 5 6 7 8 TFDS 11.75 5.08 2.54 1.43 8 7 6 5 1.8 2.54 0.63 8.25 0.63 1+0.1 (2x) 4.13 2.2 1 1 2.54 2 2.54 3 4 5.08 Dimensions in mm Ordering Information Order Part Number TFDS4500-TR3 TFDT4500-TR3 Qty/Reel 750 Pieces 750 Pieces All TEMIC transceivers are classified as IEC 825-1 Accessible Emission Limit (AEL) Class 1 based upon the current proposed draft scheduled to go into effect on January 1, 1997. AEC Class 1 LED devices are considered eye safe. TEMIC Semiconductors S-51444--Rev. A, 14-Jul-97 7 Pre-Release Information |
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